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x t january 2000 intel and pentium are registered trademarks of intel corporation. spread spectrum modulation is licensed under us patent no. 54 88627, lexmark international, inc. american microsystems, inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 1.31.00 )6 0rwkhuerdug&orfn*hqhudwru,& ,62 1.0 features generates clocks required for intel ? i820 based desktop and workstation systems, including: four enabled 2.5v 133/100mhz cpu front side bus (fsb) clocks two 2.5v cpu/2 clocks for synchronous memory seven enabled 3.3v pci bus clocks and one free-running pci clock four enabled 3.3v 66mhz agp clocks three 2.5v 16.67mhz apic bus clocks two 3.3v 14.318mhz ref clocks one 3.3v 48mhz usb clock cpu clock cycle C cycle jitter < 150ps p-p non-linear spread-spectrum modulation (-0.5% at 31.5khz) supports test mode and tristate output control separate cpu-enable, pci-enable and power-down inputs with glitch-free stop clock controls on all clocks for clock control and power management figure 1: block diagram crystal oscillator ck48 ref_0:1 apic_0:2 sel_0:1 xout cpu/2_0:1 pci_1:7 xin cpu_stop# pci_stop# pwr_dwn# delay FS6261-01 vdd_r vss_r vdd_a vss_a vss_c vdd_c vdd_p vss_p vdd_48 vss_48 (2.5v outputs) sel_133/100# pci_f ss_en# 6 or 8 cpu_0:3 vss_c2 vdd_c2 3 or 4 vss_66 vdd_66 ck66_0:3 delay 1? or 2 2 delay pll pll 3 or 4 2.0 description the FS6261-01 is a cmos clock generator ic designed for high-speed motherboard applications. two different frequencies can be selected for the cpu clocks via two sel pins. glitch-free stop clock control of the cpu, agp (66mhz) and pci clocks is provided. a low current power-down mode is available for mobile applications. separate clock buffers provide for a 2.5v voltage range on the cpu_0:3, cpu/2_0:1 and apic_0:2 clocks. figure 2: pin configuration 1 48 2 3 4 5 6 7 8 47 46 45 44 43 42 41 ref_0 ref_1 vss_r xin xout pci_1 cpu_2 cpu_3 vss_a vdd_a apic_0 9 10 11 12 13 14 15 16 pci_2 vss_p pci_3 pci_4 pci_5 pci_6 vdd_p pci_7 17 18 19 20 21 22 23 vss_p ck66_0 ck66_1 40 39 38 37 36 35 34 33 vdd cpu_1 cpu_0 vdd_c vss_c 32 31 30 29 sel_0 ss_en# pci_stop# cpu_stop# vss 24 FS6261-01 vss_p pci_f vdd_p pwr_dwn# vss_c vdd_c apic_1 (2.5v outputs) 25 26 27 28 54 53 52 51 50 49 56 55 vss_48 vdd_48 ck48 vdd_r vss_66 vdd_66 vss_66 ck66_2 ck66_3 vdd_66 sel133/100# sel_1 vss_c2 cpu/2_0 cpu/2_1 vdd_c2 apic_2 56-pin ssop table 1: cpu/pci frequency selection sel_133/100# sel_1 sel_0 cpu (mhz) pci (mhz) 0 0 0 tristate tristate 0 0 1 (reserved) (reserved) 0 1 0 100 33.33 0 1 1 100 33.33 1 0 0 xin/2 xin/6 1 0 1 (reserved) (reserved) 1 1 0 133 33.33 1 1 1 133 33.33
x t january 2000 1.31.00 2 )6 0rwkhuerdug&orfn*hqhudwru,& ,62 table 2: pin descriptions key: ai = analog input; ao = analog output; di = digital input; di u = input with internal pull-up; di d = input with internal pull-down; dio = digital input/output; di-3 = three-level digital input, do = digital output; p = power/ground; # = active-low pin pin type name description 53, 54, 55 do apic_0:2 three low-skew (<250ps @ 1.25v) 2.5v 16.67mhz clock outputs for apic bus timing. apic clocks are synchronous with cpu clocks but lag the cpu clocks by 1.5 to 4ns. 30 do ck48 one 3.3v 48mhz clock output for universal serial bus (usb) timing 21, 22, 25, 26 do ck66_0:3 four 3.3v 66mhz agp clock outputs. ck66 clocks are synchronous with cpu clocks but lag the cpu clocks by 0 to 1.5ns. 41, 42, 45, 46 do cpu_0:3 four low-skew 2.5v 133/100mhz cpu clock outputs for host frequencies 49, 50 do cpu/2_0:1 two low-skew 2.5v clock outputs at half the cpu clock frequencies (66/50mhz) 36 di u cpu_stop# cpu_0:3 and ck66_0:3 clock output enable. asynchronous, active-low disable stops all cpu and ck66 clocks in the low state. 9, 11, 12, 14, 15, 17, 18 do pci_1:7 seven 3.3v pci clock outputs. pci clocks are synchronous with cpu clocks but lag the ck66 clocks by 1.5 to 4ns. 8 do pci_f one free-running 3.3v pci clock output 37 di u pci_stop# pci_1:7 clock output enable. asynchronous, active-low disable stops all pci clocks in the low state. 35 di u pwr_dwn# asynchronous active-low power-down signal shuts down oscillator, all plls, puts all clocks in low state. clock re-enable latency of 3ms. 2, 3 do ref_0:1 two buffered outputs of the 14.318mhz reference clock 32, 33 di u sel_0:1 two frequency select inputs (see table 4) 28 di sel_133/100# selects 133mhz or 100mhz cpu frequency (pull-up/pull-down must be provided externally) 34 di u ss_en# spread spectrum enable. active-low enable turns on the spread spectrum feature; a logic-high turns off the spread spectrum modulation. 39 p vdd 3.3v 10% 31 p vdd_48 power supply for 3.3v ck48 clock output 23, 27 p vdd_66 power supply for 3.3v ck66_0:3 clock outputs 56 p vdd_a power supply for 2.5v apic_0:2 clock outputs 43, 47 p vdd_c power supply for 2.5v cpu_0:3 clock outputs 51 p vdd_c2 power supply for 2.5v cpu/2_0:1 clock outputs 10, 16 p vdd_p power supply for 3.3v pci_1:7 and pci_f clock outputs 4 p vdd_r power supply for 3.3v ref_0:1 clock outputs 38 p vss ground 29 p vss_48 ground for ck48 clock outputs 20, 24 p vss_66 ground for ck66_0:3 clock outputs 52 p vss_a ground for apic_0:2 clock outputs 40, 44 p vss_c ground for cpu_0:3 clock outputs 48 p vss_c2 ground for cpu/2_0:1 clock outputs 7, 13, 19 p vss_p ground for pci_1:7 and pci_f clock outputs 1 p vss_r ground for ref_0:1 clock outputs 5 ai xin 14.318mhz crystal oscillator input. xin can be driven by an external frequency source. 6 ao xout 14.318mhz crystal oscillator output
x t january 2000 1.31.00 3 )6 0rwkhuerdug&orfn*hqhudwru,& ,62 table 3: actual clock frequencies note: spread spectrum disabled clock target (mhz) actual (mhz) deviation (ppm) 16.67 (with cpu = 133.3) 16.6634 -195.92 apic_0:2 16.67 (with cpu = 100.0) 16.6661 -36.657 133.33 133.3072 -195.92 cpu_0:3 100.00 99.9963 -36.657 66.67 66.6536 -195.92 cpu/2_0:1 50.00 49.9982 -36.657 33.33 (with cpu = 133.3) 33.3268 -195.92 pci_1:7, pci_f 33.33 (with cpu = 100.0) 33.3321 -36.657 66.67 (with cpu = 133.3) 66.6536 -195.92 ck66_0:3 66.67 (with cpu = 100.0) 66.6642 -36.657 ck48 (1) 48 48.0080 +167 (1) 48mhz usb clock is required to be 167ppm off from 48.000mhz to conform to usb requirements. 3.0 programming information table 4: function/clock enable configuration control inputs clock outputs (mhz) sel_ 133/100# sel_1 sel_0 pwr_ dwn# cpu_ stop# pci_ stop# ref_0:1 cpu_0:3 cpu/2_ 0:1 pci_f pci_1:7 apic_ 0:2 ck48 ck66_ 0:3 0001xxtristatetristatetristatetristatetristatetristatetristatetristate 001111 (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) 01011114.3181005033.3333.3316.67tristate66.67 01111114.3181005033.3333.3316.674866.67 100111xin xin2 xin4 xin8 xin8 xin16 xin2 xin4 101111 (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) 11011114.318 133.33 66.67 33.33 33.33 16.67 tristate 66.67 11111114.318 133.33 66.67 33.33 33.33 16.67 48 66.67 x x x 0 x x low low low low low low low low 1 0 0 14.318 low running 33.33 low 16.67 48 low 1 0 1 14.318 low running 33.33 33.33 16.67 48 low 1 1 0 14.318 running running 33.33 low 16.67 48 66.67 sel_0:1 and sel_133/100# 1 0 or sel_0:1 1 01 1 1 1 14.318 running running 33.33 33.33 16.67 48 66.67
x t january 2000 1.31.00 4 )6 0rwkhuerdug&orfn*hqhudwru,& ,62 3.1 sel_1, sel_0 these two input pins can either tristate the output drivers, select the test mode frequency, or choose the cpu fre- quencies. both the sel_1 and sel_0 pins have pull-ups that default the cpu output frequency to either 100mhz or 133mhz, depending on the state of the sel_133/100# pin. these pins should be fixed at a logic state before power-up occurs. 3.2 sel_133/100# this pin is an active-low lvttl input that switches be- tween a 133mhz or a 100mhz system (cpu) clock. a pull-up or pull-down must be provided externally and this pin should be fixed at a logic state before power-up oc- curs. 4.0 clock latency all clock outputs are stopped in the low state, and are started so that the first high pulse is a full pulse width. all clocks complete a full period on transitions between run- ning (enabled) and stopped (disabled) to ensure glitch- free stop clock control. all enabled clocks will continue to run while disabled clocks are stopped. the clock enable signals are as- sumed to be asynchronous inputs relative to clock out- puts. enable signals are synchronized to their respective clocks by this device. the cpu and pci clocks will tran- sition between running and stopped according to table 5. 4.1 power-up latency power-up latency is defined as the time from the moment when pwr_dwn# goes inactive (a rising edge) to when the first valid clocks are driven from the device. upon re- lease of pwr_dwn#, external circuitry should allow a minimum of 3ms for the plls to lock before enabling any clocks. 4.1.1 pwr_dwn# the pwr_dwn# signal is an asynchronous, active-low lvttl input that puts the device in a low power inactive state without removing power from the device. all internal clocks are turned off, and all clock outputs are held low. powering down occurs in less than two pci clocks from the falling edge of pwr_dwn# to when all clock outputs are forced low. the ref and ck48 clocks are brought low as soon as possible. 4.2 clock enable latency clock enable latency is defined in the number of rising edges of free-running pci clocks between when the en- able signal becomes active (a rising edge) to when the first valid clock is driven from the device. 4.2.1 cpu_stop# the cpu_stop# pin is an active-low lvttl input pin that disables the cpu_0:3 and ck66_0:3 clocks for low power operation. cpu_stop# can be asserted asyn- chronously, and the stop clock control is glitch-free, in that the cpu clock must complete a full cycle before the clock is stopped low. one rising edge of the pci_f clock is allowed before the cpu and ck66 clocks are enabled or disabled. 4.2.2 pci_stop# the pci_stop# pin is an active-low lvttl input pin that disables the pci_1:7 clocks for low power operation, ex- cept for the pci_f clock. the pci_f is a free-running clock, and will continue to run even if all other pci clocks have stopped. pci_stop# can be asserted asynchro- nously, and the stop-clock control is glitch-free, in that the pci clock must complete a full cycle before the clock is stopped low. only one rising edge of the pci_f clock is allowed after the pci_stop# signal is enabled/disabled. table 5: latency table signal signal state pci clock enable latency 0 disabled 1 cpu_stop# 1 enabled 1 0 disabled 1 pci_stop# 1 enabled 1 0 power off 2 (max.) pwr_dwn# 1 power on 3ms
x t january 2000 1.31.00 5 )6 0rwkhuerdug&orfn*hqhudwru,& ,62 figure 2: cpu_stop# timing pci_f cpu (133mhz) cpu_ stop# cpu (100mhz) figure 3: pci_stop# timing pci_f pci_ stop# pci_1:7 figure 4: pwr_dwn# timing pci_f pwr_ dwn# cpu (133mhz) pci_1:7 cpu (100mhz) vco crystal oscillator shaded regions in the crystal oscillator and vco waveforms indicate that the clock is valid and the crystal oscillator and vco are active.
x t january 2000 1.31.00 6 )6 0rwkhuerdug&orfn*hqhudwru,& ,62 5.0 spread spectrum modulation to limit peak emi emissions, high-speed motherboard designs now require the reduction of the peak harmonic energy contained in the system bus frequencies. a re- duction in the peak energy of a specific frequency can be accomplished by spreading the energy over a limited range of frequencies through a technique known as spread spectrum clocking. in this technique, a generated clock frequency is dithered in a tightly controlled sweep near the clock frequency using a predetermined modula- tion profile and period. figure 5: spectral energy distribution spread- spectrum clock non-spread clock d e (1- d )f nom f nom the amount of emi reduction is directly related to three parameters: the modulation percentage, the frequency of the modulation, and the modulation profile. 5.1 modulation percentage the modulation percentage d , is typically 0.5% of the center frequency (denoted here as f nom ). the modulation percentage determines the range of frequencies the spectral energy is distributed over. for a 100mhz clock frequency, a 0.5% modulation sweeps the clock fre- quency between 99.5mhz and 100.5mhz. if the sweep is symmetrical around the center frequency, the technique is known as center-spread modulation. however, a circuit that is designed for a 100mhz reference may not have enough timing margin to support a clock greater then 100mhz. the clock frequency can instead be modulated between f nom , and (1- d ) f nom, ; the technique is known as down-spread modulation. for a d of C0.5%, the clock will sweep between 99.5mhz and 100mhz. a small degrada- tion in circuit performance may be noticed, as the clock frequency now averages 99.75mhz. 5.2 modulation frequency the frequency of modulation, noted as f m , describes how fast the center frequency sweeps between f nom , and (1- d ) f nom, . typical modulation frequencies must be greater than 30khz (above the audio band) but small enough to not upset system timing. since a tracking pll cannot instantaneously update the output clock to match a modulated input clock, any accumulation of the difference in phase between the modulated input clock and a track- ing pll output clock is called tracking skew. the result- ing phase error will decrease the timing margins in any successive circuitry. 5.3 modulation profile the modulation profile determines the shape of the spectral energy distribution by defining the time that the clock spends at a specific frequency. the longer a clock remains at a specific frequency, the larger the energy concentration at that frequency. a sinusoidal modulation spends a large portion of time between f nom , and (1- d ) f nom , resulting in large energy peaks at the edges of the spectral energy distribution. a linear modulation, such as a triangle profile, improves the spectral distribution but also exhibits energy peaking at the edges. a non-linear modulation profile, known as the hershey kiss profile offers the best distribution of spectral energy. figure 6: modulation profiles time (1- d )f nom f nom 1/f m time (1- d )f nom f nom 1/f m the type of modulation profile used will also impact tracking skew. the maximum frequency change occurs at the profile limits where the modulation changes the slew rate polarity. to track the sudden reversal in clock fre- quency, the downstream pll must have a large loop bandwidth.
x t january 2000 1.31.00 7 )6 0rwkhuerdug&orfn*hqhudwru,& ,62 compared to the profile limits the modulation slew rate is relatively slow between the limits, allowing the down- stream pll a chance to reduce the tracking skew. the ability of the downstream pll to catch up is determined by the loop transfer function phase angle. spread spectrum clocking can be shown to have a negli- gible effect on cycle-to-cycle jitter performance. any in- crease in jitter is less than 1ps when d <1% and f m <50khz. careful design of downstream plls can en- sure that tracking skew is minimized. to have less than 100ps of tracking skew, a downstream pll should have a loop bandwidth greater than 1mhz, and a phase angle less than 0.1 . figure 7 shows the tracking skew of a downstream pll with a loop bandwidth of 1.5mhz and a phase angle of 0.26 following a non-linear profile-modulated 100mhz input clock with a d =-0.5% and an f m =31.2khz. figure 7: pll tracking skew 100 80 60 40 20 0 20 40 60 80 100 pll tracking skew time [us] skew [ps] 5.4 spread spectrum enable the active-low lvttl ss_en# input pin enables spread spectrum modulation of the cpu and pci clocks. when ss_en# is a logic-high, the spread spectrum modulation of these clocks is disabled. if ss_en# is a logic-low, spread spectrum modulation is enabled. a pull-up on this pin disables spread spectrum modula- tion by default. figure 8: actual modulation profile 65 60 55 50 45 40 35 30 25 20 15 10 5 0 99.6 99.5 99.7 99.8 99.9 100 frequency (mhz) 1/f m (s)
x t january 2000 1.31.00 8 )6 0rwkhuerdug&orfn*hqhudwru,& ,62 6.0 electrical specifications table 6: absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. exposure to maximum rati ng conditions for extended conditions may affect device performance, functionality, and reliability. parameter symbol min. max. units supply voltage (v ss = ground) v dd v ss -0.5 7 v input voltage, dc v i v ss -0.5 v dd +0.5 v output voltage, dc v o v ss -0.5 v dd +0.5 v input clamp current, dc (v i < 0 or v i > v dd )i ik -50 50 ma output clamp current, dc (v i < 0 or v i > v dd )i ok -50 50 ma storage temperature range (non-condensing) t s -65 150 c ambient temperature range, under bias t a -55 125 c junction temperature t j 125 c lead temperature (soldering, 10s) 260 c input static discharge voltage protection (mil-std 883e, method 3015.7) 2 kv caution: electrostatic sensitive device permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy ele c- trostatic discharge. table 7: operating conditions parameter symbol conditions/description min. typ. max. units core (vdd) @ 3.3v 5% 3.135 3.3 3.465 clock buffers (vdd_p, vdd_r, vdd_66, vdd_48) @ 3.3v 5% 3.135 3.3 3.465 supply voltage v dd clock buffers (vdd_a, vdd_c, vdd_c2) @ 2.5v 5% 2.375 2.5 2.625 v operating temperature range t a 070c crystal resonator frequency f xtal 14.316 14.318 14.32 mhz crystal resonator load capacitance c xl xin, xout pins 13.5 18 22.5 pf apic_0:2 10 20 cpu_0:3 10 20 cpu/2_0:3 10 20 pci_f, pci_1:7 10 30 ck48 10 20 ck66_0:3 10 30 load capacitance c l ref_0:1 10 20 pf
x t january 2000 1.31.00 9 )6 0rwkhuerdug&orfn*hqhudwru,& ,62 table 8: dc electrical specifications unless otherwise stated, all power supplies = 3.3v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 s from typical. negative currents indicate current flows out of the device. parameter symbol conditions/description min. typ. max. units overall f cpu = 133mhz; sel_0:1 = 11 vdd_a = vdd_c = vdd_c2 = 3.465v 120 f cpu = 133mhz; sel_0:1 = 11 vdd_a = vdd_c = vdd_c2 = 2.625v 88 f cpu = 100mhz; sel_0:1 = 11 vdd_a = vdd_c = vdd_c2 = 3.465v 120 supply current, dynamic, with loaded outputs i dd f cpu = 100mhz; sel_0:1 = 11 vdd_a = vdd_c = vdd_c2 = 2.625v 86 ma pwr_dwn# low vdd_a = vdd_c = vdd_c2 = 3.465v 12 supply current, static i dds pwr_dwn# low vdd_a = vdd_c = vdd_c2 = 2.625v 8 m a digital inputs (cpu_stop#, pci_stop#, pwr_dwn#, sel_0:1, ss_en#) high-level input voltage v ih 2.0 v dd +0.3 v low-level input voltage v il v ss -0.3 0.8 v high-level input current i ih 5 m a low-level input current (pull-up) i il v il = 0.4v -2 -0.8 m a digital inputs (sel_133/100#) high-level input voltage v ih 2.0 v dd +0.3 v low-level input voltage v il v ss -0.3 0.8 v input leakage current i i -5 +5 m a crystal oscillator feedback (xin) threshold bias voltage v th 1.5 v high-level input current i ih v ih = 3.3v 32 m a low-level input current i il v il = 0v -32 m a crystal loading capacitance * c l(xtal) as seen by an external crystal connected to xin and xout 13.5 18 22.5 pf input loading capacitance * c l(xin) as seen by an external clock driver on xout; xin unconnected 36 pf crystal oscillator drive (xout) high level output source current i oh v i = 3.3v, v o = 0v -8.0 ma low level output sink current i ol v i = 0v, v o = 3.3v 8.7 ma
x t january 2000 1.31.00 10 )6 0rwkhuerdug&orfn*hqhudwru,& ,62 table 8: dc electrical specifications, continued unless otherwise stated, all power supplies = 3.3v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 s from typical. negative currents indicate current flows out of the device. parameter symbol conditions/description min. typ. max. units cpu_0:3, cpu/2_0:1, apic_0:2 clock outputs (2.5v type 1 clock buffer) i oh min vdd_c, vdd_c2, vdd_a = 2.375v, v o = 1.0v -27 high level output source current i oh max vdd_c, vdd_c2, vdd_a = 2.625v, v o = 2.375v -27 ma i ol min vdd_c, vdd_c2, vdd_a = 2.375v, v o = 1.2v 27 low level output sink current i ol max vdd_c, vdd_c2, vdd_a = 2.625v, v o = 0.3v 30 ma z ol measured at 1.25v, output driving low 13.5 23 45 output impedance z oh measured at 1.25v, output driving high 13.5 25 45 w tristate output current i oz -10 10 m a short circuit output source current i sch v o = 0v; shorted for 30s, max. -56 ma short circuit output sink current i scl v o = 2.5v; shorted for 30s, max. 58 ma ref_0:1, ck48 clock outputs (3.3v type 3 clock buffer) i oh min vdd_r, vdd_48 = 3.135v, v o = 1.0v -29 high-level output source current i oh max vdd_r, vdd_48 = 3.465v, v o = 3.135v -23 ma i ol min vdd_r, vdd_48 = 3.135v, v o = 1.95v 29 low-level output sink current i ol max vdd_r, vdd_48 = 3.465v, v o = 0.4v 27 ma z ol measured at 1.65v, output driving low 20 45 60 output impedance z oh measured at 1.65v, output driving high 20 46 60 w tristate output current i oz -10 10 m a short circuit output source current i osh v o = 0v; shorted for 30s, max. -41 ma short circuit output sink current i osl v o = 3.3v; shorted for 30s, max. 40 ma pci_1:7, pci_f, ck66_0:1 clock outputs (3.3v type 5 clock buffer) i oh min vdd_p, vdd_66 = 3.135v, v o = 1.0v -33 high level output source current i oh max vdd_p, vdd_66 = 3.465v, v o = 3.135v -33 ma i ol min vdd_p, vdd_66 = 3.135v, v o = 1.95v 30 low level output sink current i ol max vdd_p, vdd_66 = 3.465v, v o = 0.4v 38 ma z ol measured at 1.65v, output driving low 12 29 55 output impedance z oh measured at 1.65v, output driving high 12 37 55 w tristate output current i oz -10 10 m a short circuit output source current i osh v o = 0v; shorted for 30s, max. -51 ma short circuit output sink current i osl v o = 3.3v; shorted for 30s, max. 62 ma
x t january 2000 1.31.00 11 )6 0rwkhuerdug&orfn*hqhudwru,& ,62 table 9: ac timing specifications unless otherwise stated, all power supplies = 3.3v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 s from typical. negative currents indicate current flows out of the device. spread spectrum modulation is disabled except for rise/fall time measurements. 133mhz 100mhz parameter symbol conditions/description min. typ. max. min. typ. max. units overall spread spectrum modulation frequency * f m ss_en# low 31.5 31.5 khz spread spectrum modulation index* d m ss_en# low -0.5 -0.5 % cpu @ 1.25v, c l =20pf to ck66 @ 1.5v, c l =30pf (rising edges) 00.31.500.41.5 ck66 @ 1.5v, c l =30pf to pci @ 1.5v, c l =30pf (rising edges) 1.5 2.9 4.0 1.5 3.1 4.0 clock offset t pd cpu @ 1.25v, c l =20pf to apic @ 1.25v, c l =20pf (rising edges) 1.5 2.3 4.0 1.5 3.3 4.0 ns tristate enable delay * t dzl, t dzh sel_0:1 and sel_133/100#=0 1.0 10 1.0 10 ns tristate disable delay * t dzl, t dzh sel_0:1 and sel_133/100#=0 1.0 10 1.0 10 ns clock stabilization (on power-up) * t stb via pwr_dwn# 3.0 3.0 ms apic_0:2 clock output (2.5v type 1 clock buffer) duty cycle * d t ratio of high pulse width to one clock period, measured at 1.5v 45 50 55 45 50 55 % clock skew * t skw apic to apic @ 1.25v, c l =20pf -70 -70 jitter, long term ( s y ( t )) * t j(lt) on rising edges 500 m s apart at 1.25v relative to an ideal clock, c l =20pf, all plls active 204 122 ps jitter, period (peak-peak) * t j( d p) from rising edge to rising edge at 1.25v, c l =20pf, all plls active 82 88 ps t r min measured @ 0.4v C 2.0v; c l =10pf 1.2 1.2 rise time * t r max measured @ 0.4v C 2.0v; c l =20pf 1.5 1.5 ns t f min measured @ 2.0v C 0.4v; c l =10pf 1.8 1.5 fall time * t f max measured @ 2.0v C 0.4v; c l =20pf 2.1 1.8 ns cpu/2_0:1 clock outputs (2.5v type 1 clock buffer) duty cycle * d t ratio of high pulse width to one clock period, measured at 1.5v 45 52 55 45 52 55 % clock skew * t skw cpu/2 to cpu/2 @ 1.25v, c l =20pf +10 +10 jitter, long term ( s y ( t )) * t j(lt) on rising edges 500 m s apart at 1.25v relative to an ideal clock, c l =20pf, all plls active 136 122 ps jitter, period (peak-peak) * t j( d p) from rising edge to rising edge at 1.25v, c l =20pf, all plls active 108 112 ps t r min measured @ 0.4v C 2.0v; c l =10pf 0.9 0.8 rise time * t r max measured @ 0.4v C 2.0v; c l =20pf 1.1 1.1 ns t f min measured @ 2.0v C 0.4v; c l =10pf 1.0 1.0 fall time * t f max measured @ 2.0v C 0.4v; c l =20pf 1.2 1.2 ns
x t january 2000 1.31.00 12 )6 0rwkhuerdug&orfn*hqhudwru,& ,62 table 9: ac timing specifications, continued unless otherwise stated, all power supplies = 3.3v, no load on any output, and ambient temperature t a = 25c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 s from typical. spread spectrum modulation is disabled except for rise/fall time measurements. 133mhz 100mhz parameter symbol conditions/description min. typ. max. min. typ. max. units cpu_0:3 clock outputs (2.5v type 1 clock buffer) duty cycle * d t ratio of high pulse width to one clock period, measured at 1.5v 45 49 55 45 49 55 % clock skew * t skw cpu to cpu @ 1.25v, c l =20pf +60 +60 jitter, long term ( s y ( t )) * t j(lt) on rising edges 500 m s apart at 1.25v relative to an ideal clock, c l =20pf, all plls active 136 134 ps jitter, period (peak-peak) * t j( d p) from rising edge to rising edge at 1.25v, c l =20pf, all plls active 123 97 ps t r min measured @ 0.4v C 2.0v; c l =10pf 1.1 0.9 rise time * t r max measured @ 0.4v C 2.0v; c l =20pf 1.4 1.4 ns t f min measured @ 2.0v C 0.4v; c l =10pf 1.0 0.9 fall time * t f max measured @ 2.0v C 0.4v; c l =20pf 1.1 1.2 ns enable delay * t dlh via cpu_stop# 1.0 8.0 1.0 8.0 ns disable delay * t dhl via cpu_stop# 1.0 8.0 1.0 8.0 ns ref_0:1 clock outputs (3.3v type 3 clock buffer) duty cycle * d t ratio of high pulse width to one clock period, measured at 1.5v 45 50 55 45 50 55 % jitter, long term ( s y ( t )) * t j(lt) on rising edges 500 m s apart at 1.5v relative to an ideal clock, c l =20pf, all plls active 27 23 ps jitter, period (peak-peak) * t j( d p) from rising edge to rising edge at 1.5v, c l =20pf, all plls active 177 111 ps t r min measured @ 0.4v C 2.4v; c l =10pf 0.9 0.9 rise time * t r max measured @ 0.4v C 2.4v; c l =20pf 1.4 1.4 ns t f min measured @ 2.4v C 0.4v; c l =10pf 1.0 1.0 fall time * t f max measured @ 2.4v C 0.4v; c l =20pf 1.6 1.6 ns ck48 clock output (3.3v type 3 clock buffer) duty cycle * d t ratio of high pulse width to one clock period, measured at 1.5v 45 51 55 45 51 55 % jitter, long term ( s y ( t )) * t j(lt) on rising edges 500 m s apart at 1.5v relative to an ideal clock, c l =20pf, all plls active 244 246 ps jitter, period (peak-peak) * t j( d p) from rising edge to rising edge at 1.5v, c l =20pf, all plls active 143 202 ps t r min measured @ 0.4v C 2.4v; c l =10pf 0.8 0.8 rise time * t r max measured @ 0.4v C 2.4v; c l =20pf 1.3 1.3 ns t f min measured @ 2.4v C 0.4v; c l =10pf 0.9 0.9 fall time * t f max measured @ 2.4v C 0.4v; c l =20pf 1.4 1.4 ns
x t january 2000 1.31.00 13 )6 0rwkhuerdug&orfn*hqhudwru,& ,62 table 9: ac timing specifications, continued unless otherwise stated, all power supplies = 3.3v, no load on any output, and ambient temperature t a = 25c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 s from typical. spread spectrum modulation is disabled except for rise/fall time measurements. 133mhz 100mhz parameter symbol conditions/description min. typ. max. min. typ. max. units pci_1:7, pci_f clock outputs (3.3v type 5 clock buffer) duty cycle * d t ratio of high pulse width to one clock period, measured at 1.5v 45 47 55 45 50 55 % pci_f to pci @ 1.5v, c l =30pf +660 +660 clock skew * t skw pci to pci @ 1.5v, c l =30pf +60 +60 ps jitter, long term ( s y ( t )) * t j(lt) on rising edges 500 m s apart at 1.5v relative to an ideal clock, c l =30pf, all plls active 220 131 ps jitter, period (peak-peak) * t j( d p) from rising edge to rising edge at 1.5v, c l =30pf, all plls active 76 95 ps t r min measured @ 0.4v C 2.4v; c l =10pf 1.2 1.3 rise time * t r max measured @ 0.4v C 2.4v; c l =30pf 1.8 1.8 ns t f min measured @ 2.4v C 0.4v; c l =10pf 1.3 1.2 fall time * t f max measured @ 2.4v C 0.4v; c l =30pf 1.6 1.5 ns enable delay * t dlh via pci_stop# 1.0 8.0 1.0 8.0 ns disable delay * t dhl via pci_stop# 1.0 8.0 1.0 8.0 ns ck66_0:3 clock outputs (3.3v type 5 clock buffer) duty cycle * d t ratio of high pulse width to one clock period, measured at 1.5v 45 52 55 45 51 55 % clock skew * t skw ck66 to ck66 @ 1.5v, c l =30pf 120 120 ps jitter, long term ( s y ( t )) * t j(lt) on rising edges 500 m s apart at 1.5v relative to an ideal clock, c l =30pf, all plls on 137 123 ps jitter, period (peak-peak) * t j( d p) from rising edge to rising edge at 1.5v, c l =30pf, all plls active 75 79 ps t r min measured @ 0.4v C 2.4v; c l =10pf 0.9 0.9 rise time * t r max measured @ 0.4v C 2.4v; c l =30pf 1.5 1.5 ns t f min measured @ 2.4v C 0.4v; c l =10pf 1.0 1.0 fall time * t f max measured @ 2.4v C 0.4v; c l =30pf 1.4 1.4 ns enable delay * t dlh via cpu_stop# 1.0 8.0 1.0 8.0 ns disable delay * t dhl via cpu_stop# 1.0 8.0 1.0 8.0 ns figure 9: clock skew diagrams t skw t skw t skw 3.3v 2.5v 1.25v 1.5v 2.5v 2.5v 1.25v 1.25v 3.3v 3.3v 1.5v 1.5v 2.5v to 3.3v clock offset 2.5v to 2.5v clock skew 3.3v to 3.3v clock skew cpu ck66 apic cpu pci ck66
x t january 2000 1.31.00 14 )6 0rwkhuerdug&orfn*hqhudwru,& ,62 figure 10: dc measurement points v ih 3.3 = 2.0v v il 3.3 = 0.8v v ol 3.3 = 0.4v v oh 3.3 = 2.4v 1.5v 3.3v v ih 2.5 = 1.7v v il 2.5 = 0.7v 2.5v v ol 2.5 = 0.4v v oh 2.5 = 2.0v 1.25v a. 3.3v clock interface b. 2.5v clock interface (device interface) (system interface) (device interface) (system interface) figure 11: timing diagrams t kh t r duty cycle t kl t kp 2.0v 1.25v 0.4v t f t kh t r duty cycle t kl t kp 2.4v 1.5v 0.4v t f a. 3.3v clock interface b. 2.5v clock interface table 10: cpu_0:3, cpu/2_0:1, apic_0:2 clock outputs high drive current (ma) low drive current (ma) voltage (v) min. typ. max. voltage (v) min. typ. max. 0 0 0 0 0 -28 -61 -107 0.1 3 7 11 0.4 -28 -61 -107 0.2 6 13 21 0.6 -28 -61 -107 0.3 9 19 30 0.8 -28 -61 -107 0.4 12 24 40 1 -27 -60 -105 0.5 15 30 48 1.2 -26 -58 -101 0.6 173556 1.4-24-53-94 0.7 193963 1.6-21-48-85 0.8 214370 1.8-17-40-73 0.9 234777 1.9-15-36-67 1 245083 2 -12-31-59 1.1 255388 2.1 -9-25-51 1.2 275693 2.2 -6-20-43 1.3 275897 2.3 -3-14-34 1.4 28 60 100 2.375 0 -9 -27 1.6 29 62 106 2.5 0 -14 1.8 29 63 110 2.625 0 2.2 29 63 111 2.375 29 63 111 2.5 63 111 2.625 111 -120 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 output voltage (v) output current (ma) 30w 50w 90w data in this table represents nominal characterization data only
x t january 2000 1.31.00 15 )6 0rwkhuerdug&orfn*hqhudwru,& ,62 table 11: ref_0:1, ck48 clock outputs high drive current (ma) low drive current (ma) voltage (v) min. typ. max. voltage (v) min. typ. max. 0 0 0 0 0 -29 -46 -99 0.4 9 13 27 1 -29 -46 -99 0.65 14 21 41 1.4 -27 -44 -94 0.85 17 26 52 1.5 -27 -43 -92 1 2029591.65-25-41-89 1.4 253776 1.8-24-39-85 1.5 263979 2 -22-36-79 1.65 27 41 84 2.4 -16 -28 -63 1.8 284388 2.6-12-22-53 1.95 29 45 92 3.135 0 -6 -23 3.135 29 45 102 3.3 0 -12 3.6 45 102 3.465 0 -120 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 00.511.522.533.5 output voltage (v) output current (ma) 30w 50w 90w data in this table represents nominal characterization data only table 12: pci_1:7, pci_f, ck66_0:3 clock outputs high drive current (ma) low drive current (ma) voltage (v) min. typ. max. voltage (v) min. typ. max. 0 0 0 0 0 -34 -59 -195 0.4 9.4 18 38 1 -33 -58 -194 0.65 14 30 64 1.4 -31 -55 -189 0.85 17.7 38 84 1.5 -30 -54 -184 1 20 43 100 1.65 -28 -52 -172 1.4 26.5 53 139 1.8 -25.5 -50 -159 1.5 28 55 148 2 -22 -46 -140 1.65 29 56 163 2.4 -14.5 -35 -100 1.8 30 57 175 2.6 -11 -28 -83 1.95 30 58 178 3.135 0 -6 -33 3.135 31 59 187 3.3 0 -19 3.6 32 59 188 3.465 0 -200 -150 -100 -50 0 50 100 150 200 0 0.5 1 1.5 2 2.5 3 3.5 output voltage (v) output current (ma) 30w 50w 90w data in this table represents nominal characterization data only
x t january 2000 1.31.00 16 )6 0rwkhuerdug&orfn*hqhudwru,& ,62 7.0 package information table 13: 56-pin ssop (0.300") package dimensions dimensions inches millimeters min. max. min. max. a 0.095 0.110 2.41 2.79 a 1 0.008 0.016 0.203 0.406 a 2 0.088 0.092 2.24 2.34 b 0.008 0.0135 0.203 0.343 c 0.005 0.010 0.127 0.254 d 0.720 0.730 18.29 18.54 e 0.292 0.299 7.42 7.59 e 0.025 bsc 0.64 bsc h 0.400 0.410 10.16 10.41 l 0.024 0.040 0.610 1.02 q 0 8 0 8 c l 7 typ. q h e all radii: 0.005" to 0.01" x t 1 56 be d a 1 seating plane base plane a 2 a table 14: 56-pin ssop (0.300") package characteristics parameter symbol conditions/description typ. units thermal impedance, junction to free-air q ja air flow = 0 m/s 81 c/w longest trace + wire 6.41 lead inductance, self l 11 shortest trace + wire 2.49 nh longest trace + wire to first adjacent trace 3.65 l 12 shortest trace + wire to first adjacent trace 1.35 longest trace + wire to next adjacent trace 2.50 lead inductance, mutual l 13 shortest trace + wire to next adjacent trace 0.90 nh longest trace + wire to v ss 0.94 lead capacitance, bulk c 11 shortest trace + wire to v ss 0.49 pf longest trace + wire to first adjacent trace 0.48 c 12 shortest trace + wire to first adjacent trace 0.20 longest trace + wire to next adjacent trace 0.04 lead capacitance, mutual c 13 shortest trace + wire to next adjacent trace 0.01 pf
x t january 2000 1.31.00 17 )6 0rwkhuerdug&orfn*hqhudwru,& ,62 8.0 ordering information table 15: device ordering codes device number ordering code package type operating temperature range shipping configuration 11565-801 48-pin (7.5mm/0.300) ssop (shrink small outline package) 0 c to 70 c (commercial) tape and reel FS6261-01 11565-811 48-pin (7.5mm/0.300) ssop (shrink small outline package) 0 c to 70 c (commercial) tubes 9.0 revision information date page description 1/31/00 11-13 updated characterization data copyright ? 1999, 2000 american microsystems, inc. devices sold by ami are covered by the warranty and patent indemnification provisions appearing in its terms of sale only. ami makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the fr eedom of the described devices from patent infringement. ami makes no warranty of merchantability or fitness for any purposes. ami re - serves the right to discontinue production and change specifications and prices at any time and without notice. amis products are intended for use in commercial applications. applications requiring extended temperature range, unusual environmental require- ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recom- mended without additional processing by ami for such applications. american microsystems, inc., 2300 buckskin rd., pocatello, id 83201, (208) 233-4690, fax (208) 234-6796, www address: http://www.amis.com e-mail: tgp@amis.com

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